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COMMERCIAL TEMPERATURE RANGE

IDT7290820 5V TIME SLOT INTERCHANGE

DIGITAL SWITCH 2,048 x 2,048

TABLE 11  FRAME INPUT OFFSET REGISTER (FOR) BITS

Name

(1)

Description

OFn2, OFn1, OFn0 These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to

(Offset Bits 2, 1 & 0) start a new frame. The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse

input signal is applied to the F0i input of the device. See Figure 5.

DLEn

(Data Latch Edge) ST-BUS

mode: DLEn = 0, if clock rising edge is at the ¾ point of the bit cell.

DLEn = 1, if when clock falling edge is at the ¾ of the bit cell.

GCI mode: DLEn = 0, if clock falling edge is at the ¾ point of the bit cell.

DLEn = 1, if when clock rising edge is at the ¾ of the bit cell.

Read/Write Address: 03

H for FOR0 register,

04H for FOR1 register,

05H for FOR2 register,

06H for FOR3 register,

Reset Value: 0000H for all FOR registers.

1514131211109876543210

OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0

FOR0 Register

1514131211109876543210

OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF52 OF51 OF50 DLE5 OF42 OF41 OF40 DLE4

FOR1 Register

1514131211109876543210

OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10 OF92 OF91 OF90 DLE9 OF82 OF81 OF80 DLE8

FOR2 Register

1514131211109876543210

OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12

FOR3 Register

NOTE:

1. n denotes an input stream number from 0 to 15.

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 26 27

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