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COMMERCIAL TEMPERATURE RANGE

IDT7290820 5V TIME SLOT INTERCHANGE

DIGITAL SWITCH 2,048 x 2,048

JTAG SUPPORT

The IDT7290820 JTAG interface conforms to the Boundary-Scan standard

IEEE-1149.1. This standard specifies a design-for-testability technique called

Boundary-Scan Test (BST). The operation of the boundary-scan circuitry is

controlled by an external test access port (TAP) Controller.

TEST ACCESS PORT (TAP)

The Test Access Port (TAP) provides access to the test functions of the

IDT7290820. It consists of three input pins and one output pin.

•Test Clock Input (TCK)

TCK provides the clock for the test logic. The TCK does not interfere with

any on-chip clock and thus remain independent. The TCK permits shifting of test

data into or out of the Boundary-Scan register cells concurrently with the

operation of the device and without interfering with the on-chip logic.

•Test Mode Select Input (TMS)

The logic signals received at the TMS input are interpreted by the TAP

Controller to control the test operations. The TMS signals are sampled at the

rising edge of the TCK pulse. This pin is internally pulled to Vcc when it is not

driven from an external source.

•Test Data Input (TDI)

Serial input data applied to this port is fed either into the instruction register

or into a test data register, depending on the sequence previously applied to

the TMS input. Both registers are described in a subsequent section. The

received input data is sampled at the rising edge of TCK pulses. This pin is

internally pulled to Vcc when it is not driven from an external source.

•Test Data Output (TDO)

Depending on the sequence previously applied to the TMS input, the

contents of either the instruction register or data register are serially shifted out

towards the TDO. The data out of the TDO is clocked on the falling edge of the

TCK pulses. When no data is shifted through the boundary scan cells, the TDO

driver is set to a high impedance state.

•Test Reset (TRST)

Reset the JTAG scan structure. This pin is internally pulled to VCC.

INSTRUCTION REGISTER

In accordance with the IEEE 1149.1 standard, the IDT7290820 uses public

instructions. The IDT7290820 JTAG Interface contains a two-bit instruction

when the TAP Controller is in its shifted-IR state. Subsequently, the instructions

are decoded to achieve two basic functions: to select the test data register that

may operate while the instruction is current, and to define the serial test data

Value Instruction Function

11 Bypass Select ByPass Register

10 Sample/Period Select Boundry Scan Register

01 Sample/Period Select Boundry Scan Register

00 EXTEST Select Boundry Scan Register

TEST DATA REGISTER

As specified in IEEE 1149.1, the IDT7290820 JTAG Interface contains two

test data registers:

•The Boundary-Scan register

The Boundary-Scan register consists of a series of Boundary-Scan cells

arranged to form a scan path around the boundary of the IDT7290820 core

logic.

•The Bypass Register

The Bypass register is a single stage shift register that provides a one-bit

path from TDI to its TDO. The IDT7290820 boundary scan register contains

118 bits. Bit 0 in Table 15 Boundary Scan Register is the first bit clocked out.

All three-state enable bits are active high.

JTAG Instruction Register Decoding

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 26 27

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Abit TX5 Manuel d'utilisateur Page 17

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