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COMMERCIAL TEMPERATURE RANGE

IDT7290820 5V TIME SLOT INTERCHANGE

DIGITAL SWITCH 2,048 x 2,048

PIN DESCRIPTION

SYMBOL NAME I/O DESCRIPTION

GND Ground. Ground Rail.

Vcc Vcc +5.0 Volt Power Supply.

TX0-15

(1)

TX Output 0 to 15 O Serial data output stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon

(Three-state Outputs) the value programmed at bits DR0-1 in the IMS register.

RX0-15

(1)

RX Input 0 to 15 I Serial data input stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon

the value programmed at bits DR0-1 in the IMS register.

F0i

(1)

Frame Pulse I When the WFPS pin is LOW, this input accepts and automatically identifies frame synchronization signals formatted

according to ST-BUS

and GCI specifications. When the WFPS pin is HIGH, this pin accepts a negative frame

pulse which conforms to WFPS formats.

FE/HCLK

(1)

Frame Evaluation/ I When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK

HCLK Clock (4.096 MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode.

CLK

(1)

Clock I Serial clock for shifting data in/out on the serial streams (RX/TX 0-15). Depending upon the value programmed

at bits DR0-1 in the IMS register, this input accepts a 4.096, 8.192 or 16.384 MHz clock.

TMS Test Mode Select I JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-

up when not driven.

TDI Test Serial Data In I JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up

when not driven.

TDO Test Serial Data Out O JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when

JTAG scan is not enabled.

TCK

(1)

Test Clock I Provides the clock to the JTAG test logic. This pin is pulled high by an internal pull-up when not driven.

TRST Test Reset I Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled

by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure

that the IDT7290820 is in the normal functional mode.

(1)

Internal Connection I Connect to GND for normal operation. This pin must be LOW for the IDT7290820 to function normally and to

comply with IEEE 1114 (JTAG) boundary scan requirements.

RESET

(1)

Device Reset I This input (active LOW) puts the IDT7290820 in its reset state that clears the device internal counters, registers

(Schmitt Trigger Input) and brings TX0-15 and microport data outputs to a high-impedance state. The time constant for a power up

reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET

pin must be held LOW for a minimum of 100ns to reset the device.

WFPS

(1)

Wide Frame I When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in

Pulse Select ST-BUS

/GCI mode.

A0-7

(1)

Address 0-7 I When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal

memories.

DS/RD

(1)

Data Strobe/Read I For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with CS

to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This

active LOW input works in conjunction with CS to enable the read and write operations. For Intel multiplexed bus

operation, this input is RD. This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.

R/W / WR

(1)

Read/Write / Write I In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls

the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus

operation, this input is WR. This active LOW input is used with RD to control the data bus (AD0-7) lines as inputs.

(1)

Chip Select I Active LOW input used by a microprocessor to activate the microprocessor port of IDT7290820.

AS/ALE

(1)

Address Strobe or I This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed

Latch Enable bus operation, connect this pin to ground. This pin is pulled low by an internal pull-down when not driven.

(1)

CPU Interface Mode I When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor

port is in non-multiplexed mode. This pin is pulled low by an internal pull-down when not driven.

AD0-7

(1)

Address/Data Bus 0 to 7 I/O These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins

are also the input address bits of the microprocessor port.

NOTE:

1. These pins are 5V tolerant.

1 2 3 4 5 6 7 8 9 ... 26 27

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